Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide various user-defined features. In certain applications, configuration data may be stored in an external non-volatile memory such as a flash memory. The configuration data may be loaded from the external non-volatile memory into the PLD and programmed into volatile configuration memory of the PLD.
External memory devices may be implemented with a variety of different interface characteristics, such as different bus speeds, different data bus widths, or other characteristics. For example, memory devices available from Macronix International Co., Ltd, can be read serially or in two or four-bit bus widths. A PLD can read data from such a device by transmitting the appropriate read command for the data width to the memory device. However, in order for a PLD to successfully communicate with different types or different brands of external memory devices, the PLD should know the particular interface characteristics of the memory device before attempting to read data from it (e.g., in what word width the data is stored in the memory device).
For example, in one approach, external configuration signals (e.g., supply voltages or signals received from another device) may be provided to one or more dedicated external configuration pins of a PLD. Logic states of the external signals received at the dedicated external pins may be used to identify the interface characteristics of the external memory device to the PLD.
Unfortunately, external PLD pins are typically very limited in supply, and developers often prefer to use external PLD pins for general-purpose user logic (e.g., as input/output (I/O) pins) rather than as dedicated memory interface configuration pins. Moreover, external PLD pins that are used to identify interface characteristics often cannot be easily reused for general-purpose user logic.
In another approach, a PLD may issue different known read commands to an external memory device and determine which of the read commands causes the external memory device to respond successfully. However, this “trial-and-error” approach is inefficient in that it requires the PLD to issue various different types of read commands with no assurance that any of the read commands will actually cause the external memory device to respond. As a result, there is a need for an improved approach for identifying external memory device interface characteristics to PLDs.